Scientists, including those of Indian origin, have built a new 3D chip using carbon nano-tubes that can store and process massive amounts of data, paving the way for smaller, faster and more energy-efficient devices. Computers today comprise different chips cobbled together. There is a chip for computing and a separate chip for data storage, and the connections between the two are limited.
As applications analyse increasingly massive volumes of data, the limited rate at which data can be moved between different chips is creating a critical communication “bottleneck.” With limited real estate on the chip, there is not enough room to place them side-by-side, even as they have been miniaturised – a phenomenon known as Moore’s Law.
To make matters worse, the underlying devices, transistors made from silicon, are no longer improving at the historic rate that they have for decades. The new prototype chip, developed by researchers at Stanford University and Massachusetts Institute of Technology (MIT) in the US, is a radical change from today’s chips. It uses multiple nanotechnologies, together with a new computer architecture, to reverse both of these trends.
Instead of relying on silicon-based devices, the chip uses carbon nanotubes, which are sheets of 2D graphene formed into nanocylinders, and resistive random-access memory (RRAM) cells, a type of non-volatile memory that operates by changing the resistance of a solid dielectric material.
The researchers, including Subhasish Mitra and Krishna Saraswat from Stanford, integrated over one million RRAM cells and two million carbon nanotube field-effect transistors, making the most complex nanoelectronic system ever made with emerging nanotechnologies. The RRAM and carbon nanotubes are built vertically over one another, making a new, dense 3D computer architecture with interleaving layers of logic and memory.
By inserting ultradense wires between these layers, this 3D architecture promises to address the communication bottleneck. However, such an architecture is not possible with existing silicon-based technology, according to Max Shulaker from MIT.
“Circuits today are 2D, since building conventional silicon transistors involves extremely high temperatures of over 1,000 degrees Celsius,” said Shulaker. “If you then build a second layer of silicon circuits on top, that high temperature will damage the bottom layer of circuits,” he said.
The key in this work is that carbon nanotube circuits and RRAM memory can be fabricated at much lower temperatures, below 200 degrees Celsius. “This means they can be built up in layers without harming the circuits beneath,” he said. This provides several simultaneous benefits for future computing systems.
“The devices are better: Logic made from carbon nano-tubes can be an order of magnitude more energy-efficient compared to today’s logic made from silicon, and similarly, RRAM can be denser, faster, and more energy-efficient compared to DRAM,” Wong said, referring to a conventional memory known as dynamic random-access memory.