IIT-Delhi researchers build homegrown graphics chip for low-cost devices

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The current system runs on a Spartan-7 Field Programmable Gate Array (FPGA), rather than as a standalone silicon chip.

The team developed a programmable graphics processor architecture capable of graphics rendering, with the hardware described in Register Transfer Language (RTL) and implemented on the FPGA platform.

M Tech students Nammi Akash and M Ravi Teja led the project under the guidance of professors Jayadeva and Kaushik Saha of the Department of Electrical Engineering.

“Our objective was to create a compact but genuinely programmable graphics-processing architecture suitable for FPGA implementation and future ASIC realisation. We hope such indigenous hardware systems can support affordable digital-access platforms and contribute meaningfully towards bridging the digital divide,” said Akash, one of the researchers.

Designed for embedded applications

Teja said that the hardware architecture is a scalable, programmable graphics processor IP suitable for applications such as industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers and other affordable embedded visualisation systems.

The design could be implemented on programmable hardware such as FPGAs or converted into an Application-Specific Integrated Circuit (ASIC), the researchers said.

An ASIC would involve manufacturing the processor design as a dedicated silicon chip. The current work, however, remains at the FPGA demonstration stage.

The researchers said they are now exploring an 8–16-core vector-style graphics processor architecture, along with an optimised compiler and graphics software toolchain. The longer-term plan includes developing a proof of concept using a 65-nanometre ASIC process.

The choice of a mature 65-nm semiconductor process targets applications where cost, power consumption and practical deployment matter more than the extreme performance associated with newer semiconductor nodes, the researchers said.

From student project to processor architecture

Jayadeva said the work shows the potential of indigenous programmable graphics hardware for affordable, socially useful computing platforms, adding that many innovations were needed to realise the design on a standard FPGA board.

“The project encourages students to integrate arithmetic hardware, programmable architectures, compilers, and embedded systems thinking within a unified framework while also addressing wider societal accessibility challenges,” Saha said.

The researchers said the next stage will focus on scaling the architecture, developing the supporting software ecosystem and evaluating its eventual implementation as an ASIC.