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Friday, September 24, 2021

IIT Delhi professor develops device to reduce frequency of charging electronic goods

The research has been done in collaboration with the National University of Singapore.

By: Express Web Desk | New Delhi |
July 30, 2021 1:55:16 pm
The frequent charging of wireless electronic devices such as mobile phones, IoT devices, etc would be significantly reduced with the proposed device.

A professor of Indian Institute of Technology, Delhi (IIT-D) has developed a device for high-density magnetic memory which could reduce the frequency of charging wireless electronic devices, such as mobile phones, in the future. The research has been done in collaboration with the National University of Singapore (NUS).

“As we are moving toward a data-driven age, there is a need for faster and very low power computing. Memories play a crucial role in this, as for faster processing of data, the CPU rapidly reads and writes on the memory. The main memory, i.e. the Random-access memories (RAMs), are most commonly used in modern computer architecture…They are fast but volatile, which means they require a constant supply of power, this consumes lots of energy. But if these could be made non-volatile, then computing could be made more energy efficient,” IIT-D said in a statement.

“Spintronics memories like spin-transfer torque magnetoresistive RAM (STT-MRAM) and spin-orbit torque magnetoresistive RAM (SOT-MRAM) are inherently non-volatile. They consume no power at standby. Also, their operation speeds are comparable to RAMs. Hence, these spintronics memories are the most potential candidates for replacing current electronic RAMs,” it added.

Professor Rahul Mishra from the Centre for Applied Research in Electronics (CARE), IIT Delhi and Professor Hyunsoo Yang from NUS “experimentally demonstrated” a “possible solution for achieving higher integration density in SOT-MRAMs”.

The work was published in Volume 15, Issue 2 of the journal ‘Physical Review Applied’ in February this year.

“We demonstrated a shared write channel based multibit SOT cell scheme, which reduces the number of transistors required per bit. This cell design requires half the area compared to conventional SOT-MRAM, thus almost doubling the area efficiency of the memory chip,” said Mishra.

To make the design feasible, the team designed a magnetic memory device, which can be programmed by application of gate voltage, IIT-D said. The gate voltage was used to “migrate oxygen ions in the device which resulted in modulation of the spin current polarity”, therefore, cells can now be “written individually” and hence obtained a “full-fledged, working area-efficient SOT memory”.

“The results of this work could eventually help to develop low power electronic devices. The frequent charging of wireless electronic devices such as mobile phones, IoT devices, etc would be significantly reduced with the proposed device. It would be especially useful for industrial applications where sensors are put in locations, which are not easy to access. Low power and high-density memory devices would not only be helpful in reducing global energy footprint, but the saved energy can also be used for extra computational tasks,” said Mishra.

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